1. Technical Field
Example embodiments of the present invention relate to a chip stack package and a method of manufacturing the chip stack package. More particularly, example embodiments of the present invention relate to a chip stack package including a plurality of chips stacked on a wiring substrate and a method of manufacturing the chip stack package.
2. Description of the Related Art
Generally, semiconductor devices are manufactured by a fabrication process, an electrical die sorting (EDS) process, and a packaging process. The fabrication process typically comprises forming electric circuits including electric elements on a semiconductor substrate such as a silicon wafer. The electrical die sorting (EDS) process includes inspecting electrical properties of chips formed by the fabrication process. The packaging process includes sealing the chips with resin such as epoxy and sorting the chips.
Nowadays, a chip stack package is used as one type of packaging technology to increase the packaging efficiency of the chips per unit volume. To manufacture the chip stack package, recesses are formed at upper surface portions of the chips, respectively. Then, each of the recesses is filled up with a conductive material by a plating process to form a plug in the recesses. After a solder is coated on the plug, a lower surface of each of the chips is planarized until the plug is exposed. The chips including the plugs are stacked on a silicon substrate or a printed circuit board (PCB). The chips are bonded to form the chip stack package.
However, because the plug is formed in each of the chips in order to manufacture the chip stack package, a time required to perform the plating process for forming the plugs in the chips may be greatly increased. Additionally, a void may be generated within the plug. Further, uniformity of the shape and dimensions of the plug may be deteriorated. The chips may not be aligned accurately when the chips are stacked on the silicon substrate or the PCB because the solder coated on the plug protrudes from the upper surface of the chip. Thus, not only a contact problem between the solder of one chip and the plug of an adjacent chip but also tilting of the multi-stacked chips may occur.
Further, when the chips have different sizes and the plugs are spaced apart from one another, it may be difficult to manufacture the chip stack package. The present invention addresses these and other disadvantages of conventional methods.